The present invention relates generally to memory devices and in particular the present invention relates to tri-stating an output buffer during initialization of a synchronous memory.
Memory devices are typically provided as internal storage areas in the computer. The term xe2x80x9cmemoryxe2x80x9d identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory. One type is RAM (random-access memory). This is typically used as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM, and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. Many modern PCS have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in modems because it enables the modem manufacturer to support new protocols as they become standardized.
A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU""s bus and is capable of running at 100 MHZ, about three times faster than conventional FPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. SDRAM""s can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory.
Generally, all synchronized memory devices require system circuits within the device to be initialized before the memory can be powered up for reliable operation. The initialization process generally includes setting registers for proper operations. It takes a period of time to complete the initialization process. During this time, the memory device can have unknown internal signals and data states. As a result of the unknown states, non-valid data may be sent through output buffers of the memory system causing the system to read faulty data.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory that avoids erroneous output while internal initialization is taking place.
The above-mentioned problems with non-valid data being sent during initialization and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, the present invention provides a synchronous memory device that comprises a memory array, an output buffer that outputs data from the memory array, a tri-state logic circuit that selectively tri-states the output buffer and control circuitry to signal the tri-state logic circuit to tri-state the output buffer during memory initialization. The synchronous memory device can also include a pair of DQMASK connections to signal the tri-state logic circuit to tri-state the output buffer manually with external commands.
In another embodiment, a synchronous flash memory device comprises, a memory array of non-volatile memory cells, an output buffer to output data from the memory array, a tri-state logic circuit to selectively tri-state the output buffer during initialization and control circuitry to signal the tri-state logic circuit to tri-state the output buffer during memory initialization.
In another embodiment, a memory system comprises an external processor and a synchronous memory that is coupled to the external processor. The synchronous memory comprises a memory array, an output buffer to output data from the memory array, a tri-state logic circuit to selectively tri-state the output buffer and control circuitry to signal the tri-state logic circuit to tri-state the output buffer during memory initialization. The memory system can also include the external processor providing a read status command to the memory to determine the status of memory initialization.
A method of operating a non-volatile memory that includes tri-stating an output buffer of the memory while the memory is being initialized. One method including starting initialization of the memory, tri-stating an output buffer of the memory, finishing initialization of the memory and returning the output buffer to normal operation after initialization of memory is completed.
Another method of operating a memory system includes starting initialization of a memory, tri-stating an output buffer during initialization of the memory, polling the memory to verify the status of initialization, and allowing an external processor to access the memory upon verification of completion of memory initialization. Optionally, the method can include overriding the tri-state condition of the output buffer to signal the external processor that initialization is occurring.